The conventional approach to IC circuit design and manufacturing is founded on a basic concept of maintaining a constant separation of the transmission lines.
FIG. 3 is an example of design a circuit layout based on the conventional double layer fabrication process.
In a plan view of such a design, device element regions 1, 2 are for forming such device elements as gate electrodes. In this type of IC circuitry, the transmission lines 3-8 in the first layer are connected to similar lines 9-16 in the second layer by means of the throughholes 17.
Associated with such transmission lines hereinafter referred to as the lines) 3-16, are line capacitance regions created by the influence of the neighboring lines. For example, on both sides of the line 3 on the same plane as the line 3, there exist lines 4-7 sharing the first layer in common, and thereby creating capacitance regions among the three lines concerned.
FIG. 4 is a plan view of three lines 20, 21 and 22, all of which are disposed on one plane and have the line width W1. The lines 20 and 21 are separated by a distance d1, and the lines 21 and 22 are separated by a distance d2. In the conventional designs, the spacing d1 and d2 as well as the width W1 are usually set to be about 2 .mu.m. The line material is an aluminum film of about 0.6 to 0.8 .mu.m thickness, and the interlayer distance of separation is set at about 0.8 .mu.m.
If the lines are regarded as simple parallel strips, the capacitance, C, is given by an expression: EQU C=.epsilon..times..epsilon..sub.0 .times.(circuit area).times.(spacing)
where .epsilon. is the relative interlayer dielectric constant and .epsilon..sub.0 is the dielectric constant in a vacuum.
For the shape of the line shown in FIG. 5, the bottom capacitance C1 per unit length of the line 21, which has the dimensions of W1=2 .mu.m, film thickness=0.8 .mu.m and d1=d2=2 .mu.m is: EQU C1=.epsilon..times..epsilon..sub.0 .times.(2.div.0.8)
and similarly the side capacitance C2 per unit length between the lines 20 and 21 is: EQU C2=.epsilon..times..epsilon..sub.0 .times.(0.8.div.2)
and similarly the side capacitance C3 per unit length between the lines 21 and 22 (not shown) is: EQU C3=.epsilon..times..epsilon..sub.0 .times.(0.8.div.2)
thereby yielding the ratio of the capacitances in the bottom region to the side region as 2.5:0.8.
On the other hand, the gate delay time in IC circuits depends on the driving power of the gate and on the gate capacitance. For the same driving power, the smaller the gate capacitance, easier it is to increase the gate speed. The circuit capacitance in IC circuits, in the meantime, is the total sum of all the gate input capacities and the line capacitance. Therefore, the lesser the line capacitance, the lesser the circuit capacity and easier it is to increase the gate speed.
However, because the conventional IC circuit designs are based on constant line spacings, the line capacitance becomes a serious source of noise generation caused by interline interferences in such long length line components as clock lines, bus lines and analogue signal lines.
The progress in fabrication technology has made it possible to decrease the line spacing as low as 1.2 .mu.m in some trial devices.
As shown in FIG. 6, for the same line geometry but having decreased the line spacing from 2.0 to 1.2 .mu.m, the capacitances per unit length of line 21 for the bottom and the side surfaces corresponding to FIG. 4, are:
.epsilon..times..epsilon..sub.0 .times.1.5 for the bottom capacitance C1' and PA1 .epsilon..times..epsilon..sub.0 .times.1.3 for the side capacitance C2' (also for C3' between the lines 21 and 22). PA1 (1) the side surface capacitance contribution to the line capacitance becomes large, and it becomes more difficult to decrease the proportion of the side surface capacitance in the line capacitance as the interline spacing is decreased; PA1 (2) with the increase in the side surface capacitance, there is a corresponding increase in the line capacitance in the equivalent circuit, leading to an increase in the delay time; and
As can be seen from the above figures, the proportion of the side capacitance in the line capacitance is fairly large. Therefore, with the progress in microcircuit fabrication technology, the effect of the side capacitance becomes even more significant and it becomes increasingly important to decrease the line capacitance.
For example, suppose an inverter is connected to the signal line 21 shown in FIG. 4, then its equivalent circuit is as illustrated in FIG. 7 (a). The line capacitance between the lines 20 and 21 appears as interline capacitance C1 and that between the lines 21 and 22 (not shown) as interline capacitance C2.
FIG. 7 (b) shows the case of the line 20 being at the supply voltage and the line 22 is grounded; if both lines are grounded, the equivalent circuit appears as shown in FIG. 7 (c). Comparing the circuits in FIG. 7 (b) and FIG. 7 (c), the line capacitive loads on the output terminal of the inverter are significantly different from each other. This means that the line capacitance itself can vary with the signal level in the neighboring lines. This can cause signal transmission delays within the internal IC circuitry, and in some cases, can lead to incorrect operation of the circuit itself. This will be further amplified below.
Variations in the signal level, between the line voltage and the ground in the neighboring lines 20 and 22, of the signal line 21 are the same as the voltage variations in one electrode of the capacitances C1 and C2.
Therefore, it is evident that the voltage of the load line 21 is affected by the voltage variations of the neighboring lines, the effect being larger the higher the capacitance of the neighboring lines. The effect is less if other capacitance (bottom capacitance of the lines and the gate input capacitance connected to the lines) are high.
Further, the capacitive effects are greater in noise-sensitive LSI circuits, for analogue and ECL circuits for example, than in CMOS circuits which have relatively large tolerances for noise. In these noise-sensitive devices, there are cases of erroneous actions being activated by interline capacitive coupling effects. As the technique of microcircuit fabrication develop, and interline spacing becomes small, there are more noises generated as a results of increasing capacitive coupling, leading to increased incidences of errors caused by capacitive couplings.
To summarize the problems created by the progress in microcircuit fabrication:
(3) it leads to stronger interline capacitive coupling, to higher noise levels, thus leading to faulty operation of a device.